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19-1909; Rev 0; 6/01
Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout
General Description
The MAX9121/MAX9122 quad low-voltage differential signaling (LVDS) differential line receivers are ideal for applications requiring high data rates, low power, and low noise. The MAX9121/MAX9122 are guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlledimpedance media of approximately 100. The transmission media may be printed circuit (PC) board traces or cables. The MAX9121/MAX9122 accept four LVDS differential inputs and translate them to LVCMOS outputs. The MAX9122 features integrated parallel termination resistors (nominally 107), which eliminate the requirement for four discrete termination resistors and reduce stub lengths. The MAX9121 inputs are high impedance and require an external termination resistor when used in a point-to-point connection. The devices support a wide common-mode input range of 0.05V to 2.35V, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or parallel terminated. The EN and EN inputs control the high-impedance output. The enables are common to all four receivers. Inputs conform to the ANSI TIA/EIA644 LVDS standard. Flow-through pinout simplifies PC board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS outputs. The MAX9121/ MAX9122 operate from a single +3.3V supply, and are specified for operation from -40C to +85C. These devices are available in 16-pin TSSOP and SO packages. Refer to the MAX9123 data sheet for a quad LVDS line driver with flow-through pinout.
KIT ATION EVALU E AILABL AV
____________________________Features
o Integrated Termination Eliminates Four External Resistors (MAX9122) o Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk o Pin Compatible with DS90LV048A o Guaranteed 500Mbps Data Rate o 300ps Pulse Skew (max) o Conform to ANSI TIA/EIA-644 LVDS Standard o Single +3.3V Supply o Fail-Safe Circuit
MAX9121/MAX9122
Ordering Information
PART MAX9121EUE MAX9121ESE MAX9122EUE MAX9122ESE TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 SO 16 TSSOP 16 SO
Pin Configuration appears at end of data sheet.
Typical Application Circuit
LVDS SIGNALS
TX
107
RX
Applications
Digital Copiers Laser Printers Cellular Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches/Routers Backplane Interconnect Clock Distribution
LVTTL/LVCMOS DATA INPUT TX 107 RX
LVTTL/LVCMOS DATA OUTPUT
TX
107
RX
TX
107
RX
MAX9123
MAX9122
100 SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
________________________________________________________________ Maxim Integrated Products
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V EN, EN to GND ...........................................-0.3V to (VCC + 0.3V) OUT_ to GND .............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above +70C) .........755mW 16-Pin SO (derate 8.7mW/C above +70C)................696mW Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model, IN_+, IN_-) ....................................8kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LVDS INPUTS (IN_+, IN_-) Differential Input High Threshold Differential Input Low Threshold Input Current (MAX9121) Power-Off Input Current (MAX9121) Input Resistor 1 Input Resistor 2 Differential Input Resistance (MAX9122) LVCMOS/LVTTL OUTPUTS (OUT_) IOH = -4.0mA (MAX9121) Output High Voltage (Table 1) VOH IOH = -4.0mA (MAX9122) Output Low Voltage Output Short-Circuit Current Output High-Impedance Current VOL IOS IOZ Open, undriven short, or undriven 100 parallel termination VID = +100mV Open or undriven short VID = +100mV 2.7 2.7 2.7 2.7 -15 -10 3.2 3.2 3.2 3.2 0.1 0.25 -120 +10 V mA A V VTH VTL IIN_+, IIN_IINOFF RIN1 RIN2 RDIFF 0.1V VID 0.6V 0.6V IOL = +4.0mA, VID = -100mV Enabled, VID = 0.1V, VOUT_ = 0 (Note 2) Disabled, VOUT = 0 or VCC
2
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout
DC ELECTRICAL CHARACTERISTICS (continued)
(V CC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LOGIC INPUTS (EN, EN) Input High Voltage Input Low Voltage Input Current SUPPLY Supply Current Disabled Supply Current ICC ICCZ Enabled, inputs open Disabled, inputs open 9 0.07 15 0.5 mA mA VIH VIL IIN VIN_ = VCC or 0 2.0 0 -15 VCC 0.8 15 V V A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9121/MAX9122
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew [tPHLD tPLHD] (Note 5) Differential Channel-to-Channel Skew (Note 6) Differential Part-to-Part Skew (Note 7) Differential Part-to-Part Skew (Note 8) Rise-Time Fall-Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency (Note 9) SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 All channels switching 250 300 0.55 0.54 MIN 1.2 1.2 TYP 1.93 1.79 140 MAX 2.7 2.7 300 400 0.8 1.5 1.0 1.0 14 14 70 70 UNITS ns ns ps ps ns ns ns ns ns ns ns ns MHz
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V |VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40C to +85C. Typical values are at VCC = +3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25C, unless otherwise noted.) (Notes 3, 4) Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: tSKD1 is the magnitude difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|. Note 6: tSKD2 is the magnitude difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same part. Note 7: tSKD3 is the magnitude difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5C of each other. Note 8: tSKD4 is the magnitude difference of any differential propagation delays between parts operating over rated conditions. Note 9: fMAX generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, VOH = +1.3V, VOL = +1.1V, MAX9121/MAX9122 output criteria: 60% to 40% duty cycle, VOL = 0.4V (max), VOH = 2.7V (min), load = 15pF.
Typical Operating Characteristics
(VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CL = 15pF, TA = +25C, unless otherwise noted.) (Figures 2 and 3)
SUPPLY CURRENT vs. FREQUENCY
MAX9121/22 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX9121/22 toc02
DIFFERENTIAL THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
DIFFERENTIAL THRESHOLD VOLTAGE (mV)
MAX9121/22 toc03
40
11.00 10.50 SUPPLY CURRENT (mA) 10.00 9.50 9.00 8.50 8.00 7.50 7.00
50
SUPPLY CURRENT (mA)
30
ALL CHANNELS SWITCHING
40
30
20
20
10 ONE SWITCHING 0 0.01 0.1 1 10 100 1000 FREQUENCY (MHz)
10
0 -40 -15 10 35 60 85 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 TEMPERATURE (C)
OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
MAX9121/22 toc04
OUTPUT HIGH-IMPEDANCE CURRENT vs. SUPPLY VOLTAGE
OUTPUT HIGH-IMPEDANCE CURRENT (nA)
MAX9121/22 toc05
OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
MAX9121/22 toc06
-95 OUTPUT SHORT-CIRCUIT CURRENT (mA) -90 -85 -80 -75 -70 -65 3.0 3.3 SUPPLY VOLTAGE (V)
1.30
3.7
1.25
OUTPUT HIGH VOLTAGE (V)
3.5
3.3
1.20
3.1
1.15
2.9
1.10 3.6 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
2.7 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout
Typical Operating Characteristics (continued)
(VCC = +3.3V, VCM = +1.2V, |VID| = 0.2V, CL = 15pF, TA = +25C, unless otherwise noted.) (Figures 2 and 3)
OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
MAX9121/22 toc07
MAX9121/MAX9122
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9121/22 toc08
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9121/22 toc09
100 99 OUTPUT LOW VOLTAGE (mV) 98 97 96 95 94 93 92 3.0 3.3 SUPPLY VOLTAGE (V)
2.20 DIFFERENTIAL PROPAGATION DELAY (ns) 2.10 2.00 tPHLD 1.90 1.80 1.70 1.60 3.0 3.3 SUPPLY VOLTAGE (V)
2.10
tPHLD 1.90
tPLHD 1.70
tPLHD
3.6
1.50 3.6 -40 -15 10 35 60 85 TEMPERATURE (C)
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
MAX9121/22 toc10
DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE
MAX9121/22 toc11
DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE
MAX9121/22 toc12
2.50 DIFFERENTIAL PROPAGATION DELAY (ns)
2.2 DIFFERENTIAL PROPAGATION DELAY (ns) 2.1 2.0 1.9 1.8 1.7 1.6 1.5 tPLHD tPHLD
200 DIFFERENTIAL PULSE SKEW (ps)
2.25 tPHLD
175
2.00
150
1.75
tPLHD
125
1.50
1.25 -0.5 0 0.5 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE (V)
100 100 900 1700 2500 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 DIFFERENTIAL INPUT VOLTAGE (mV)
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9121/22 toc13
TRANSITION TIME vs. TEMPERATURE
625 TRANSITION TIME (ps) 600 575 550 525 500 475 tTHL tTLH
MAX9121/22 toc14
600
650
TRANSITION TIME (ps)
575 tTLH 550 tTHL 525
500 3.0 3.3 SUPPLY VOLTAGE (V) 3.6
450 -40 -15 10 35 60 85 TEMPERATURE (C)
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
Pin Description
PIN 1, 4, 5, 8 2, 3, 6, 7 9, 16 10, 11, 14, 15 12 13 NAME IN_IN_+ EN, EN OUT_ GND VCC Inverting Differential Receiver Inputs Noninverting Differential Receiver Inputs Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and in high impedance. LVCMOS/LVTTL Receiver Outputs Ground Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. FUNCTION
Table 1. Input/Output Function Table
ENABLES EN EN INPUTS (IN_+) - (IN_-) VID +100mV VID -100mV H L or open MAX9121 MAX9122 All other combinations of ENABLE pins Open, undriven short, or undriven 100 parallel termination Open or undriven short Don't care Z OUTPUT OUT_ H L H
Detailed Description
The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The MAX9121/MAX9122 are 500Mbps, four-channel LVDS receivers intended for high-speed, point-to-point, low-power applications. Each channel accepts an LVDS input and translates it to an LVTTL/LVCMOS output. The receiver is capable of detecting differential signals as low as 100mV and as high as 1V within an input voltage range of 0 to 2.4V. The 250mV to 400mV differential output of an LVDS driver is nominally centered around a +1.2V offset. This offset, coupled with the receiver's 0 to 2.4V input voltage range, allows an approximate 1V shift in the signal (as seen by the receiver). This allows for a difference in ground refer6
ences of the transmitter and the receiver, the commonmode effects of coupled noise, or both. The LVDS standards specify an input voltage range of 0 to +2.4V referenced to receiver ground. The MAX9122 has an integrated termination resistor that is internally connected across each receiver input. The internal termination saves board space, eases layout, and reduces stub length compared to an external termination resistor. In other words, the transmission line is terminated on the IC.
Fail-Safe
The fail-safe feature of the MAX9121/MAX9122 sets an output high when: * Inputs are open. * Inputs are undriven and shorted. * Inputs are undriven and terminated. A fail-safe circuit is important because under these conditions, noise at the inputs may switch the receiver and it may appear to the system that data is being
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
VCC RIN2 RIN2
VCC
VCC - 0.3V IN_+ RIN1 OUT_ RIN1 IN_MAX9121 IN_RDIFF RIN1 IN_+ RIN1
VCC - 0.3V
OUT_
MAX9122
Figure 1. Input with Fail-Safe Network
received. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when the LVDS driver outputs are high impedance. A short condition can occur because of a cable failure. The fail-safe input network (Figure 1) samples the input common-mode voltage and compares it to VCC - 0.3V (nominal). When the input is driven to levels specified in the LVDS standards, the input to the common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not activated. If the inputs are open or if the inputs are undriven and shorted or undriven and parallel terminated, there is no input current. In this case, a pullup resistor in the fail-safe circuit pulls both inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the output high.
close to the device as possible, with the smaller valued capacitor closest to VCC.
Differential Traces
Input trace characteristics affect the performance of the MAX9121/MAX9122. Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is also matched to this characteristic impedance. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Each channel's differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
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Applications Information
Power-Supply Bypassing
Bypass the VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
IN_+ PULSE GENERATOR** IN_50* 50* OUT_ CL
RECEIVER ENABLED 1/4 MAX9121/MAX9122
*50 REQUIRED FOR PULSE GENERATOR. **WHEN TESTING THE MAX9122, ADJUST THE PULSE GENERATOR OUTPUT TO ACCOUNT FOR INTERNAL TERMINATION RESISTOR.
Figure 2. Propagation Delay and Transition Time Test Circuit
IN_VID = 0 IN_+ tPLHD tPHLD VOH VID = (VIN_+) - (VIN_-) NOTE: VCM = (VIN- + VIN+) 2 80% 80% VID VID = 0
50%
50%
20% OUT_ tTLH tTHL
20% VOL
Figure 3. Propagation Delay and Transition Time Waveforms
Cables and Connectors
Transmission media typically have a controlled differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Termination
The MAX9122 has an integrated termination resistor connected across the inputs of each receiver. The
value of the integrated resistor is specified in the DC characteristics. The MAX9121 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance values may range between 90 to 132, depending on the characteristic impedance of the transmission medium. When using the MAX9121, minimize the distance between the input termination resistors and the MAX9121 receiver inputs. Use 1% surface-mount resistors.
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
VCC S1
IN_+ GENERATOR 50 EN EN 1/4 MAX9121/MAX9122 IN_-
RL DEVICE UNDER TEST OUT_ CL
CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS.
Figure 4. High-Impedance Delay Test Circuit
EN WHEN EN = GND OR OPEN 1.5V 1.5V
3V
0
3V 1.5V EN WHEN EN = VCC tPZL tPLZ OUTPUT WHEN VID = -100mV OUTPUT WHEN VID = +100mV 0.5V tPHZ 0.5V 50% GND tPZH VOH VCC 50% VOL 1.5V 0
Figure 5. High-Impedance Delay Waveforms
Board Layout
Because the MAX9121/MAX9122 feature a flow-through pinout, no special layout precautions are required. Keep the LVDS and any other digital signals separated from each other to reduce crosstalk. For LVDS applications, a four-layer PC board that provides separate power, ground, LVDS signals, and input signals is recommended. Isolate the input LVDS signals from each other to prevent coupling. Isolate the output LVCMOS/LVTTL signals from each other to prevent coupling. Separate the input LVDS signals from the output signals planes with the power and ground planes for best results. TRANSISTOR COUNT: 1354 PROCESS: CMOS
Chip Information
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
Functional Diagram
VCC VCC
IN1+ OUT1 IN1-
IN1+ 107 IN1OUT1
IN2+ OUT2 IN2-
IN2+ 107 IN2OUT2
IN3+ OUT3 IN3-
IN3+ 107 IN3OUT3
IN4+ OUT4 IN4-
IN4+ 107 IN4OUT4
EN EN
EN EN
MAX9121
GND GND
MAX9122
Pin Configuration
TOP VIEW
IN1- 1 IN1+ 2 IN2+ 3 IN2- 4 IN3- 5 IN3+ 6 IN4+ 7 IN4- 8 16 EN 15 OUT1 14 OUT2
MAX9121 MAX9122
13 VCC 12 GND 11 OUT3 10 OUT4 9 EN
TSSOP/SO
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout
Package Information
TSSOP,NO PADS.EPS
MAX9121/MAX9122
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Quad LVDS Line Receivers with Integrated Termination and Flow-Through Pinout MAX9121/MAX9122
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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